1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device with a processor, and in particular a semiconductor integrated circuit device with a processor allowing easy debugging.
2. Description of the Background Art
Processors such as an MPU (Microprocessor Unit) and a CPU (Central Processor Unit) are subjected to debugging such as verification of programs and verification of hardware operations. For facilitating such debugging, a debug support unit for supporting the debug operation is conventionally arranged within a processor. Particularly in a so-called xe2x80x9csystem-on-chipxe2x80x9d structure with a processor and a peripheral LSI (Large Scale Integrated Circuit Device) integrated on a single chip, complicated internal structures must be operated accurately, and the debugging is required.
FIG. 15 schematically shows internal structures of a semiconductor integrated circuit device with a processor and a debug environment in the prior art. In FIG. 15, semiconductor integrated circuit device 1 with a processor (which will be referred to as xe2x80x9cLSI with CPU 1xe2x80x9d hereinafter) includes a CPU core 2 for performing a processing instructed by an instruction applied thereto, a Read-Only Memory (ROM) 4 for storing a program, a Random Access Memory (RAM) 5 for retaining intermediate data, an IO module 6 including an I/O circuit for externally transmitting and receiving signals including data, and a Direct Memory Access Controller (DMAC) 7 for directly accessing RAM 5 to externally transmit and receive data. These CPU core 2, ROM 4, RAM 5, I/O module 6 and DMAC 7 are interconnected via an internal bus 3.
CPU core 2 is equipped with a Debug Support Unit (DSU) 2a for facilitating debugging of software (program) to be executed by CPU core 2. Debug support unit (DSU) 2a is connected to a DSU control signal line connected to a pin terminal 10, a CPU event notifying signal line connected to a pin terminal 11 for externally notifying that the CPU attains a specific internal state, and to a signal line connected to a pin terminal 12 for tracing an operation state of the CPU.
LSI with CPU 1 further includes a debugging multiplexer (MUX) 18 for connecting one of IO module 6 and internal bus 3 to an I/O terminal 13 in accordance with a test mode instructing signal TP applied via a pin terminal 19. Internal bus 3 transmits signals including data, address signals and control signals.
In LSI with CPU 1, CPU core 2 and DMAC 7 form a bus master of internal bus 3. This internal bus 3 is further connected to peripheral circuits such as a bus arbiter, which are not shown in the figure for simplicity reason.
In the debug operation, LSI with CPU 1 is coupled via pin terminals 10-12 to a DSU-adapted debug device 20 which in turn is externally arranged. DSU-adapted debug device 20 includes a controller 20a for controlling an operation of debug support unit (DSU) 2a included in CPU core 2, and a trace data storage memory 20b controlled by controller 20a to store a CPU operation state trace signal applied from debug support unit 2a via pin terminal 12. DSU-adapted debug device 20 is coupled to a computer 30 via a pin terminal 22. Accordingly, DSU-adapted debug device 20 can control the operation of the CPU included in CPU core 2 under control of computer 30, and can display the trace data stored in trace data storage memory 20b on the display screen of computer 30.
Under the debug environment, I/O terminal 13 is coupled to a logic analyzer 40 via a probe cable 42. Logic analyzer 40 monitors the logical levels of the signals on I/O terminal 13.
In the normal operation, debugging multiplexer (MUX) 18 selects and couples IO module 6 to I/O terminal 13. In the debug environment, debugging multiplexer (MUX) 18 couples internal bus 3 to I/O terminal 13 in response to activation of test mode instructing signal TP applied to pin terminal 19. By coupling internal bus 3 to I/O terminal 13 via debugging multiplexer (MUX) 8, the state of internal bus 3 is monitored by logic analyzer 40 in the debug environment. During debugging of software running on LSI with CPU 1, it is necessary to externally monitor signals that are output onto internal bus 3 in accordance with the software executed by CPU core 2, to determine whether this software is executed accurately or not. Debugging multiplexer (MUX) 18 is provided for the purpose of externally monitoring the signal value on internal bus 3.
In the debug operation, DSU-adapted debug device 20 applies control signals to debug support unit 2a via DSU control pin terminal 10, and the CPU core 2 executes the instruction under the control of these control signals. Debug support unit 2a monitors the operation state of the CPU included in CPU core 2, and applies a CPU event notifying signal to DSU-adapted debug device 20 via pin terminal 11 when the CPU attains a specific internal state specified at the time of debugging. In DSU-adapted debug device 20, when the CPU event notifying signal received via pin terminal 11 from debug support unit 2a becomes active, controller 20a applies a write instruction to trace data storage memory 20b, and the CPU operation trace information applied via pin terminal 12 from debug support unit 2a is stored therein. The CPU operation trace information stored in trace data storage memory 20b is applied to computer 30 via pin terminal 22 for display on the computer screen or the like.
Under the debug environment, debugging multiplexer (MUX) 18 couples I/O bus 3 to I/O pin 13, and logic analyzer 40 monitors the signal values on internal bus 3 via I/O pin 13 and debugging multiplexer (MUX) 18. The result of monitoring is displayed on a display screen of logic analyzer 40.
An operator checks information displayed on the display screen of computer 30 and the display screen of logic analyzer 40, and determines whether the CPU core 2 operates correctly to execute the specified instructions or not.
When an abnormality is found, the instruction causing the abnormality is identified based on the CPU operation trace information, and the debug is executed.
In this LSI with CPU 1, the bus master of internal bus 3 is CPU core 2 and direct memory access controller (DMAC) 7. When the CPU of CPU core 2 is performing arithmetic processing, direct memory access controller (DMAC) 7 accesses random access memory (RAM) 5 without adversely affecting the arithmetic operation, and executes data transfer with an external common memory or a logic/processor. In this LSI with CPU 1, the CPU included in CPU core 2 and direct memory access controller (DMAC) 7 operate in parallel with each other. Debugging relating to the parallel operation of CPU core 2 and direct memory access controller (DMAC) 7 is very important for ensuring integrity of data.
In this debug environment for the conventional LSI with CPU shown in FIG. 15, the signal values on internal bus 3 are displayed on the screen of logic analyzer 40, and the information relating to the operation state of the CPU included in CPU core 2 is displayed on the screen of computer 30. Logic analyzer 40 and computer 30 operate independently of each other. Therefore, the operation state information of the CPU included in CPU core 2 cannot be displayed on the same time base as the signal values on the internal bus. Therefore, it is difficult to correlatingly analyze the operation of CPU included in CPU core 2 and the operation state of the direct memory access controller (DMAC). Accordingly, it is extremely difficult to perform the debugging relating to the parallel operation of the CPU and the direct memory access controller (DMAC).
Since logic analyzer 40 is used, it is necessary to connect probe cable 42 to I/O pin terminals 13, and therefore I/O pin terminals 13 must be arranged on a circuit board. Therefore, logic analyzer 40 cannot be used for a Ball Grid Array (BGA) or the like in which the pin terminals are arranged under the circuit board. This results in a problem that the debugging restricts the arrangement of the I/O pin terminals in the LSI with CPU.
In the structure where a memory of a large storage capacity is integrated with CPU core 2 on the same circuit substrate, the bit width of internal bus 3 is not restricted by the number of pin terminals so that the pin width can be made sufficiently large. Meanwhile, the number of I/O pin terminals 13 and other pin terminals is restricted by the number of external pin terminals of a package of this LSI with CPU, and can be increased only to a limited value. Therefore, it is impossible to apply all the signal values on the signal lines included in internal bus 3 to logic analyzer 40, and the state of the internal bus cannot be externally monitored with sufficient accuracy.
In the actual operation, IO module 6 is used as an originally intended I/O circuit for data input/output. In the structure where LSI with CPU 1 is mounted on the board, therefore, I/O pin terminals 13 are connected to pin terminals of another device via interconnection lines, and IO module 6 is connected to IO pin terminals 13 via debugging multiplexer (MUX) 18. At the on-board level, therefore, it is impossible for logic analyzer 40 to monitor the signal values on I/O pin terminals 13 with probe cable 42 connected to I/O pin terminals 13. Thus, debugging can be performed only in the LSI with CPU alone.
Further, debugging multiplexer (MUX) 18 is provided with driver for driving I/O pin terminals 13. In the system having LSI with CPU 1, the operation frequency is in a high speed range, e.g., from 100 MHz to 300 MHz. When I/O pin terminals 13 are charged and discharged in accordance with such a fast clock, noises are caused due to electromagnetic radiation. For reducing such radiation noises, an output driver for driving I/O pin terminals 13 generally has a relatively small driving capability so that rapid charging and discharging of I/O pin terminals 13 can be suppressed. In this case, however, the charging and discharging of I/O. pin terminals 13 is performed at a relatively low speed so that a large delay occurs in signal propagation through probe cable 42. Due to this, logic analyzer 40 cannot take in fast changes in signals transmitted on internal bus 3 in accordance with the fast clock signal, via I/O pin terminals 13 and probe cable 42. Accordingly, the state of internal bus 3 cannot be externally monitored with sufficient accuracy.
An object of the invention is to provide a semiconductor integrated circuit device with a processor, which allows easy and accurate external monitoring of information required for debugging without any restriction by arrangement of pins.
Another object of the invention is to provide a semiconductor integrated circuit device with a processor, which allows external monitoring of internal bus signals without increasing the number of pins even if the internal bus has a large bit width.
According to the invention, in summary, a CPU operation trace information output pin is selectively supplied with CPU operation trace information and internal bus information.
Since the internal bus information and the processor operation information are transmitted via the same pin terminal, it is not necessary to output the internal bus information via an I/O pin terminal employed in the prior art, and the internal information can be externally monitored without increasing the number of the pin terminals and being restricted by the arrangement of pin terminals. Since the processor operation information and the internal bus information are externally transmitted via the same pin terminal, the processor operation information and the internal bus information can be analyzed by a single debug device with the time bases coincident, and the complicated debugging can be performed easily.